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| 14 GHz DIVIDE-BY-8 DYNAMIC PRESCALER UPG506B FEATURES * * * WIDE OPERATING FREQUENCY RANGE: f = 8 to 14 GHz (TA = 25C) Input Power, PIN (dBm) INPUT POWER vs. INPUT FREQUENCY TA=-25C to +75C 10 LOW PHASE NOISE GUARANTEED OPERATING TEMPERATURE RANGE (TA = -25C to +75C) Recommended Operating Region TA=+25C 0 DESCRIPTION The UPG506B is a GaAs divide-by-8 prescaler capable of operating up to 14 GHz. It is designed for use in frequency synthesizers of microwave communication systems and measurement equipment. The UPG506B is a dynamic frequency divider and employs BFL (Buffered FET Logic) circuits. The UPG506B is available in a hermetic 8-lead ceramic flat package. VDD = 3.8V VSS1=0V VSS2=-2.2V TA = -25C TA = +25C TA = +75C 0 2 4 6 8 10 12 14 16 18 -10 Input Frequency, f (GHz) ELECTRICAL CHARACTERISTICS (TA = 25C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG506B BF08 UNITS mA mA mA GHz GHz dBm dBm C/W 2.0 0 2.0 10.0 44 14 8 10.0 MIN 70 TYP 105 35 70 96 MAX 140 PART NUMBER PACKAGE OUTLINE SYMBOLS IDD ISS1 ISS2 fIN(U) fIN(L) PIN POUT RTH(CH-C) PARAMETERS AND CONDITIONS Supply Current Sink Current1 ISS1 = IDD - ISS2 Sink Current1 Upper Limit of Input Frequency at PIN = +6 dBm Lower Limit of Input Frequency at PIN = +6 dBm Input Power at f = 9 to 13 GHz Output Power at fIN = 14 GHz Thermal Resistance (Channel to Case) Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. California Eastern Laboratories UPG506B ELECTRICAL CHARACTERISTICS (TA = -25C to +75C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG506B BF08 UNITS mA mA mA GHz GHz dBm dBm 2.0 -1.0 1.0 13.2 8.2 10.0 MIN TYP 105 35 70 MAX PART NUMBER PACKAGE OUTLINE SYMBOLS IDD ISS1 ISS2 fIN(U) fIN(L) PIN POUT PARAMETERS AND CONDITIONS Supply Current Sink Current1 ISS1 = IDD - ISS2 Sink Current1 Upper Limit of Input Frequency at PIN = +6 dBm Lower Limit of Input Frequency at PIN = +6 dBm Input Power at f = 9 to 13 GHz Output Power at fIN = 14 GHz Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. ABSOLUTE MAXIMUM RATINGS1 (TA = 25C) SYMBOLS VDD - VSS1 VSS2 - VSS1 PT PIN TC TSTG PARAMETERS Supply Voltage Supply Current Total Power Dissipation2 Input Power Level CaseTemperature Storage Temperature UNITS V mA W dBm C C RATINGS 5 -5 1.5 13 -65 to +125 -65 to +175 Total Power Dissipation, PT (W) 2.0 POWER DERATING CURVES 2.5 1.5 1.0 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. TC 125C. TCASE MAX = 125C 0.5 0 0 50 100 110 150 200 250 Case Temperature, TC (C) TYPICAL PERFORMANCE CURVES (TA = 25C) SSB PHASE NOISE vs. OFFSET FROM CARRIER fIN = 12.7 GHz OUTPUT POWER vs. INPUT FREQUENCY 2.5 -70 SSB Phase Noise (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 -150 -160 10 100 1K 10K 100K 1M Output Power, POUT (dBm) PIN = +10dBm 2.0 1.5 1.0 +25C +75C 0.5 TA = -25C TA = +25C TA = +75C 0 0 2 4 6 8 10 12 14 16 18 Offset from Carrier (Hz) Input Frequency, f (GHz) UPG506B TEST CIRCUITS CONFIGURATION 1 2 Bias Supply Zo = 50 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN VSS2 (-2.2 V) 8 VSS2 10 F C OUT 1 C Zo = 50 OUT VSS1 2 NC 3 OPEN VSS1 (0 V) GND C 5 IN VDD 4 C 10 F VDD (3.8 V) VDD = 3.8 V VSS1 = 0 V (GND) VSS2 = -2.2 V C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 2 Single Positive Bias Supply Zo = 50 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN GND (0 V) VSS2 8 VSS2 OUT 1 C Zo = 50 VSS1 2 NC 3 OPEN C 2.2 V OUT C 5 IN VDD 4 C 10 F 10 F * VDD (+6 V) VDD = +6.0 V VSS2 = 0 V (GND) C: 1000 - 5000 pF Chip Capacitor * VSS1 should be connected to GND through a 2.2 V Zener Diode (RD2.2FB or IN3394). CONFIGURATION 3 Single Negative Bias Supply Zo = 50 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN VSS2 (-6 V) 8 VSS2 10 F C OUT 1 C Zo = 50 VSS1 2 C 2.2 V OUT NC 3 OPEN -6 V* 10 F C 5 IN VDD 4 VDD = 0 V (GND) VSS2 = -6 V C: 1000 - 5000 pF Chip Capacitor * For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V Zener Diode (RD2.2FB or IN3394). Notes: 1. Because of the high internal gain and gain compression of the UPG506B, the device is prone to self-oscillation in the absence of an RF input signal. This self-oscillation can be suppressed by either of the following means: * Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the selfoscillation (see the test circuit schematic). * Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0 and -9 volts will suppress the self-oscillation. Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no effect on the reliability or electrical characteristics of the device. UPG506B OUTLINE DIMENSIONS (Units in mm) UPG506B PACKAGE OUTLINE BFO8 7.00.5 1.27 1.27 1.27 0.1 0.1 0.1 1.7 MAX 8 7 6 5 10.40.5 2.6 4.40.2 1 2 0.4 5.00.2 3 4 +0.05 0.2 -0.02 LEAD CONNECTIONS 1. OUTPUT 5. INPUT 2. VSS1 6. VGG1 3. NC* 7. VGG2 4. VDD 8. VSS2 * No Connection EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES * Headquarters * 4590 Patrick Henry Drive * Santa Clara, CA 95054-1817 * (408) 988-3500 * Telex 34-6393 * FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) * Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -4/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE |
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